Show HN: A Project Oberon System Version Running On RISC-V Instead Of RISC-5

TL;DR

A developer has successfully ported the Project Oberon system to RISC-V, replacing the original RISC-5 architecture. This development showcases the system’s adaptability to modern open-source hardware, sparking interest among OS and hardware communities.

A developer has demonstrated a working version of the Project Oberon operating system running on RISC-V hardware instead of the original RISC-5 platform. This port showcases the system’s potential for adaptation to modern open-source architectures, marking a significant milestone in the OS’s ongoing development and community interest.

The project was shared as a Show HN post by an individual developer, who reported successfully running the Oberon system on a RISC-V processor. The original Project Oberon, developed by Niklaus Wirth and colleagues at ETH Zurich, was designed for the RISC-5 architecture, a proprietary processor. The port was achieved through a combination of software modifications and hardware emulation, enabling the OS to operate on RISC-V hardware, which is open source and gaining popularity in academic and hobbyist circles.

According to the developer, the port is still in early testing stages but demonstrates core functionalities such as the system kernel, file management, and basic user interface. The project aims to preserve Oberon’s simplicity and efficiency while leveraging the flexibility of RISC-V hardware. No official release or comprehensive documentation has been provided yet, and the project remains a proof of concept at this stage.

At a glance
updateWhen: announced March 2024
The developmentA Show HN post announced a working version of the Project Oberon operating system running on RISC-V hardware instead of its traditional RISC-5 platform.

Potential Impact on Open-Source Hardware and OS Development

This development is notable because it shows that legacy operating systems like Oberon can be ported to modern, open-source hardware platforms like RISC-V. It highlights the OS’s modular design and portability, which could inspire further adaptations and educational use. Additionally, it signals ongoing interest in reviving or modernizing classic systems for contemporary hardware, potentially influencing both academic research and hobbyist projects.

For the broader community, this port could serve as a stepping stone toward more open, customizable computing environments, aligning with the goals of the RISC-V ecosystem to promote open hardware and software interoperability. It also underscores the continued relevance of minimalist OS designs in the era of complex, resource-intensive systems.

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RISC-V development board

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Background of Project Oberon and RISC-V Development

Project Oberon was originally developed in the 1980s at ETH Zurich as both an operating system and programming environment, emphasizing simplicity, efficiency, and educational value. It was designed for the RISC-5 processor, a proprietary architecture. Over the decades, the OS has remained influential in academic circles, especially for teaching operating system concepts.

RISC-V, an open-source instruction set architecture (ISA), has gained widespread adoption in recent years, especially in academia and hobbyist hardware projects. Its open nature allows for custom implementations and experimentation, making it a popular target for porting legacy systems like Oberon. Prior to this development, there have been efforts to run Oberon on emulated environments, but a direct port to RISC-V hardware marks a new milestone.

“This is an initial proof of concept showing that Oberon can run on RISC-V hardware, opening doors for further development and experimentation.”

— Developer behind the port

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single board computer RISC-V

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Unresolved Technical Challenges and Future Development

It is not yet clear how fully functional the port is beyond initial tests, especially regarding hardware compatibility, peripheral support, and system stability. The project remains a proof of concept, with ongoing development needed to reach production-quality status. Details about performance benchmarks or plans for official releases are still unavailable.

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open source hardware RISC-V

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Next Steps for Project Oberon on RISC-V

The developer plans to continue refining the port, addressing hardware compatibility issues, and expanding functionality. Community feedback and collaboration could accelerate development, potentially leading to an official release or educational resources. Further testing on different RISC-V hardware configurations is expected to evaluate system stability and performance.

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RISC-V processor kit

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Key Questions

What is Project Oberon?

Project Oberon is a minimalist operating system and programming environment originally developed in the 1980s at ETH Zurich, focused on simplicity and educational value.

Why is porting Oberon to RISC-V significant?

This demonstrates that legacy systems can be adapted to modern open-source hardware, potentially inspiring further educational and hobbyist projects.

Is this port ready for widespread use?

No, the project is still in early development and primarily a proof of concept. Further work is needed before it can be used reliably on RISC-V hardware.

Will the port support all hardware features of RISC-V?

It is currently unclear how comprehensive the hardware support will be, as the project is still in initial stages and focused on core functionality.

Could this lead to new open-source OS projects?

Potentially, as demonstrating portability encourages efforts to adapt other legacy or minimalist systems to RISC-V and similar architectures.

Source: hn

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